DocumentCode :
1069960
Title :
A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology
Author :
Carusone, Anthony Chan ; Cheng, Horace ; Musa, Faisal A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Volume :
56
Issue :
8
fYear :
2009
Firstpage :
1794
Lastpage :
1806
Abstract :
Pulse-width modulation pre-emphasis (PWM-PE) is a relatively new technique for compensating severe losses in wireline channels by varying the duty cycle of the transmitted pulse. The technique has been demonstrated upto 5 Gb/s and requires high-speed digital logic to accomodate narrow pulses in the transmitted bit stream. This work targets data rates beyond 10 Gb/s and extends PWM-PE to 4-PAM signals in addition to binary mode transmission. The target speed is achieved by designing the transmitter using current mode logic (CML) blocks that combine relatively large logic swings and incomplete switching of the tail current. Implemented in a 0.13-??m CMOS process to accommodate the wide output swing of 1.2 Vpp per side, the transmitter compensates upto 30 dB loss at one-half the symbol rate and operates up to 16 Gsymbols/s.
Keywords :
CMOS logic circuits; logic gates; pulse amplitude modulation; pulse width modulation; current mode logic blocks; dual-mode pulsewidth modulation pre-emphasis transmitter; high-speed CML design methodology; loss compensation; wireline channels; CMOS; current mode logic (CML); pulse-amplitude modulation (PAM); pulsewidth modulation pre-emphasis (PWM-PE);
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2009.2024903
Filename :
5071512
Link To Document :
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