Highly vectorizable fault simulation on the Cray X-MP supercomputer

A highly vectorizable parallel fault simulation algorithm for high-speed fault simulation of combinational circuits, developed to take advantage of the specific hardware architecture of the Cray X-MP vector supercomputer, is described. The algorithm takes into account the memory organization of the supercomputer, reduces the number of vector fetches per gate simulation, and overlaps computation and I/O. Experimental results on large benchmark circuits show that very high evaluation rates (3.0-3.5×10⁹ evaluations/s) comparable to those of hardware logic simulation energies can be achieved. Speedup factors of 50-60 observed between scalar and vector execution of the simulator on the Cray X-MP/28 are reported