DocumentCode :
1070344
Title :
Radiation resistance testing of MOSFET and CMOS as a means of risk management
Author :
Tokuhiro, Akira T. ; Bertino, Massimo F.
Author_Institution :
Univ. of Missouri-Rolla, Rolla, MO, USA
Volume :
25
Issue :
3
fYear :
2002
fDate :
9/1/2002 12:00:00 AM
Firstpage :
519
Lastpage :
522
Abstract :
Whether for military, research (space, accelerator physics) and/or civilian use, risk avoidance against radiation-induced damage is not possible with COTS parts. Thus the sensible approach is risk management. We recommend a sensible risk management approach as follows: 1) know the radiation environment of the intended application to the extent possible; 2) know the effects of ionizing radiation on the component(s) of interest; 3) know the requirements of the application; 4) identify the candidate or chosen components; 5) test the components; 6) design-in safety factor margins to the extent possible.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit testing; radiation hardening (electronics); risk management; semiconductor device testing; CMOS; MOSFET; ionizing radiation; radiation environment; radiation resistance testing; radiation-induced damage; risk management; safety factor margins; test; Electron traps; Electronic components; Interface states; Ionization; Ionizing radiation; MOSFET circuits; Radiation effects; Risk management; Semiconductor materials; Testing;
fLanguage :
English
Journal_Title :
Components and Packaging Technologies, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3331
Type :
jour
DOI :
10.1109/TCAPT.2002.804782
Filename :
1159191
Link To Document :
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