Title :
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β
Author :
Yamanashi, Y. ; Tanaka, M. ; Akimoto, A. ; Park, H. ; Kamiya, Y. ; Irie, N. ; Yoshikawa, N. ; Fujimaki, A. ; Terai, H. ; Hashimoto, Y.
Author_Institution :
Yokohama Nat. Univ., Yokohama
fDate :
6/1/2007 12:00:00 AM
Abstract :
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
Keywords :
cascade networks; logic circuits; microprocessor chips; microwave circuits; pipeline arithmetic; CONNECT cell library; arithmetic logic units; control circuit design; forwarding architecture; frequency 20 GHz; frequency 25 GHz; instruction fetch; one-hot encoding; pipelined bit-serial SFQ microprocessor; power consumption; single-flux-quantum microprocessor; Arithmetic; Circuit testing; Design methodology; Encoding; Libraries; Logic; Microprocessors; Niobium; Pipeline processing; Registers; Josephson logic; SFQ circuits; microprocessors; pipelining; superconducting integrated circuits;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2007.898606