A DLL-Based Programmable Clock Multiplier in 0.18-μ m CMOS With −70 dBc Reference Spur

Author

Maulik, Prabir C. ; Mercer, Douglas A.

Author_Institution

Analog Devices Inc., Wilmington

Volume

42

Issue

8

fYear

2007

Firstpage

1642

Lastpage

1648

Abstract

This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level.

Keywords

CMOS digital integrated circuits; clocks; delay lock loops; multiplying circuits; programmable circuits; CMOS; DLL-based programmable clock multiplier; autozeroing; circuit technique; complementary metal oxide semiconductor; crosstalk reduction; frequency 150 MHz to 400 MHz; power 16 mW; reference spur level; sampling phase detector; size 0.18 mum; static phase offset reduction; Clocks; Crosstalk; Delay lines; Detectors; Frequency; Jitter; Phase detection; Phase locked loops; Sampling methods; Voltage; Autozero; chopper-stabilization; delay-locked loop (DLL); jitter; pattern jitter; phase detector; phase noise; phase-locked loop (PLL); reference spur; sample-and-hold;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.900300

Filename

4277870