Effect of the drain—Source voltage on dopant profiles obtained from the DC MOSFET profile method

An analysis was developed for the influence of a finite drain-source voltage, VDS, on dopant profiles derived from the dc MOSFET profile method. It indicates that the measured profile of uniformly doped material falls below the true profile near the surface. The effect occurs because the edge of the depletion region in the silicon is not parallel to the oxide-silicon interface for a finite VDS. For the case of uniformly doped silicon near room temperature, the analysis indicates, for reverse bias applied across the silicon, that the error in the measured dopant density due to a finite VDSis less than 1 percent if of file built-in voltage, a condition that is easily met in practice. The analysis also reveals that the profile depth determined from the depth-profile equation is a simple average of the depletion widths at the source and drain ends of the channel in uniformly doped silicon. Experimental results are presented which confirm the general trends indicated by the analysis.