Title :
Lateral DMOS Power transistor design
Author :
Colak, S. ; Singer, B. ; Stupp, E.
Author_Institution :
Philips Laboratories, Briarcliff Manor, N.Y
fDate :
4/1/1980 12:00:00 AM
Abstract :
Two dimensional analysis has been applied to model the lateral DMOST (LDMOST) transistor in the off condition. This approach predicts breakdown voltages beyond the conventional limit. Using this model, a 400 volt lateral transistor was designed, fabricated, and tested. The design values obtained from the numerical modeling, and the experimental results for a >425 volt LDMOST are presented.
Keywords :
Doping; Electric breakdown; Epitaxial layers; Geometry; Power transistors; Semiconductor process modeling; Silicon; Solid modeling; Substrates; Voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1980.25226
