CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.