Title :
P-column gate FET
Author :
Asai, Kazuyoshi ; Ishii, Yasunobu ; Kurumada, Katsuhiko
Author_Institution :
Nippon Telegraph & Telephone Public Corp., Tokyo, Japan
fDate :
5/1/1980 12:00:00 AM
Abstract :
A new structure for a GaAs JFET (P-Column Gate FET) is proposed, employing p-column shaped gates in an active n-layer on a semi-insulating substrate, where the current flows through spaces between the gate columns. It was found that Be ion implantation can produce p-column gates. The FET I-V characteristics are also presented and discussed.
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1980.25239
