DocumentCode :
1072239
Title :
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18- {\\rm \\mu}\\hbox {m} CMOS Technology
Author :
Seo, Young-Suk ; Lee, Jang-Woo ; Kim, Hong-Jung ; Yoo, Changsik ; Lee, Jae-Jin ; Jeong, Chun-Seok
Author_Institution :
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul
Volume :
56
Issue :
1
fYear :
2009
Firstpage :
6
Lastpage :
10
Abstract :
With a new 1/8-rate linear phase detector (PD), a 5-Gbit/s clock and data recovery (CDR) circuit is implemented in a digital 0.18-mum CMOS technology. The outputs of the PD have much wider pulse than those of the conventional linear PDs. Thus, the design of circuits such as the PD and charge becomes much easier, and the maximum data rate is no longer limited by the speed of phase detection. The CDR shows 6.8-ps rms and 57.4-ps peak-to-peak jitter in the recovered clock and 10-12 bit error rate for 231-1 pseudorandom binary-sequence input while consuming 144 mW from a 1.8-V supply.
Keywords :
CMOS integrated circuits; binary sequences; clock and data recovery circuits; jitter; phase detectors; random sequences; CMOS technology; bit rate 5 Gbit/s; clock circuit; data-recovery circuit; linear phase detector; peak-to-peak jitter; power 144 mW; pseudorandom binary-sequence; size 0.18 mum; voltage 1.8 V; Bit error rate; CMOS digital integrated circuits; CMOS technology; Clocks; Costs; Detectors; Frequency; Jitter; Phase detection; Space vector pulse width modulation; CMOS; Clock and data recovery (CDR) ; subrate linear phase detector (PD);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2008.2008520
Filename :
4753693
Link To Document :
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