Architecture and implementation of ICs for a DSC-HDTV video decoder system

Author

Duardo, Oded ; Knauer, Scott C. ; Mailhot, John N. ; Mondal, Kalyan ; Poon, Tommy C.

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

Volume

12

Issue

5

fYear

1992

Firstpage

22

Lastpage

27

Abstract

The architecture and implementation of the very-large-scale integrated (VLSI) video decoder subsystems in digital spectrum compatible high-definition television (DSC-HDTV) systems are discussed. The CMOS deformatter IC, which converts formatted data back to motion vectors, DCT coefficients, and coding parameters, and the motion compensator and inverse discrete transform IC, which reconstructs frames from the deformatter-decoded coefficients, are described.<>

Keywords

CMOS integrated circuits; VLSI; data compression; digital signal processing chips; high definition television; image coding; video signals; CMOS deformatter IC; DCT coefficients; DSC-HDTV; architecture; coding parameters; data conversion; digital spectrum compatible high-definition television; formatted data; frame reconstruction; inverse discrete transform IC; motion compensator; motion vectors; very-large-scale integrated; video decoder subsystems; video decoder system; Decoding; Design for disassembly; Engines; HDTV; Image coding; Image reconstruction; TV; Transmitters; Very large scale integration; Video compression;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.166709

Filename

166709