Title :
A 160 Mpixel/s IDCT processor for HDTV
Author :
Ruetz, Peter A. ; Tong, Po
Abstract :
The architecture and characteristics of a fully functional 40 MHz device that performs the 8*8 inverse discrete cosine transform (IDCT) for digital HDTV decoders are presented. The IDCT chip converts four 14-b DCT coefficients into four 11-b pixel values each cycle. Fixed-coefficient multiplier Wallace trees in which partial products are rounded before summation help compute the inner products. The 31000-gate device was implemented in a 10.5 mm die using 1 mu m CMOS array-based process.<>
Keywords :
CMOS integrated circuits; data compression; digital signal processing chips; high definition television; image coding; 1 micron; 10.5 mm; 40 MHz; CMOS array-based process; DCT coefficients; IDCT chip; IDCT processor; architecture; digital HDTV decoders; inner products; inverse discrete cosine transform; multiplier Wallace trees; CMOS process; CMOS technology; Decoding; Discrete cosine transforms; Discrete transforms; HDTV; Logic testing; Sun; Throughput; Videoconference;
Journal_Title :
Micro, IEEE
