Title :
The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI
Author :
Chatterjee, Pallab K. ; Hunter, W.R. ; Holloway, T.C. ; Lin, Y.T.
Author_Institution :
Central Research Lab, Texas Instruments, Dallas, Texas
fDate :
10/1/1980 12:00:00 AM
Abstract :
Circuit requirements of scaled devices based on noise margin, parameter variation, parasitic resistance and drift velocity saturation lead to non-constant field scaling, which predict a maximum in performance as devices are scaled. This maximum occurs at a smaller length for p-channel than for n-channel for a given scaling rule, and causes the performance of the two to approach each other at L<0.3µm. The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than n-channel devices.
Keywords :
Capacitance; Charge carrier processes; Circuits; Doping; Electron mobility; Geometry; Impurities; MOS devices; Very large scale integration; Voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/EDL.1980.25295