• DocumentCode
    1073951
  • Title

    Fabrication technology for an 80-ps normally-off GaAs MESFET logic

  • Author

    Ida, Masao ; Mizutani, Takashi ; Asai, Kazwoshi ; Uchida, Masao ; Shimada, Keiho ; Ishida, Satoru

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    28
  • Issue
    5
  • fYear
    1981
  • fDate
    5/1/1981 12:00:00 AM
  • Firstpage
    489
  • Lastpage
    493
  • Abstract
    Fabrication technology of a high-speed normally-off GaAs MESFET logic has been described. Anodic Oxidation process is applied to control epitaxial layer thickness precisely. A SiO2cap during alloying ohmic metal is used to prevent the ohmic layer surface from becoming uneven. A sloped mesa structure edge is used to avoid disconnection of metal interconnection. Electron-beam direct writing is employed to define a submicrometer gate. Applying these technologies, high-speed and small switching energy have been accomplished. The minimum delay timd and the associated switching energy were 77 ps and 75 fJ at room temperature and 51 ps and 97 fJ at 77 K.
  • Keywords
    Alloying; Delay; Epitaxial layers; Fabrication; Gallium arsenide; Logic; MESFETs; Oxidation; Thickness control; Writing;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1981.20371
  • Filename
    1481523
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1073951