DocumentCode
1074048
Title
Analysis of shared-link AXI
Author
Chang, N.Y.-C. ; Liao, Y.-Z. ; Chang, T.-S.
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu
Volume
3
Issue
4
fYear
2009
fDate
7/1/2009 12:00:00 AM
Firstpage
373
Lastpage
383
Abstract
Shared-link AXI provides decent communication performance and requires half the cost of its crossbar counterpart. The authors analysed the performance impact of the factors in a shared-link AXI system. The factors include interface buffer size, arbitration combination and task access setting (transfer mode mapping). A hybrid data locked transfer mode was also proposed to improve the performance due to AXI´s extra transition cycle. The analysis is carried out by simulating a multi-core platform with a shared-link AXI backbone running a video phone application. The performance is evaluated in terms of bandwidth utilisation, average transaction latency and system task completion time. The analysis showed that channel-independent arbitration could contribute up to 23.2´ of bandwidth utilisation and completion time difference. Moreover, the analysis suggests that the proposed hybrid data locked mode should be used only by long access latency devices. Such setting resulted in up to 21.1´ completion time reduction compared with the setting without the hybrid data locked mode. The design options in shared-link AXI bus are also discussed.
Keywords
logic design; multiprocessor interconnection networks; system buses; system-on-chip; bandwidth utilisation; channel-independent arbitration; hybrid data locked mode; hybrid data locked transfer mode; interface buffer size; multicore platform; shared-link AXI bus; system task completion time; transfer mode mapping; video phone;
fLanguage
English
Journal_Title
Computers & Digital Techniques, IET
Publisher
iet
ISSN
1751-8601
Type
jour
DOI
10.1049/iet-cdt.2008.0097
Filename
5074335
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