DocumentCode :
1074514
Title :
An Approach for Adaptive DRAM Temperature and Power Management
Author :
Liu, Song ; Zhang, Yu ; Memik, Seda O. ; Memik, Gokhan
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
Volume :
18
Issue :
4
fYear :
2010
fDate :
4/1/2010 12:00:00 AM
Firstpage :
684
Lastpage :
688
Abstract :
High-performance DRAMs are providing increasing memory access bandwidth to processors, which is leading to high power consumption and operating temperature in DRAM chips. In this paper, we propose a customized low-power technique for high-performance DRAM systems to improve DRAM page hit rate by buffering write operations that may incur page misses. This approach reduces DRAM system power consumption and temperature without any performance penalty. We combine the throughput-aware page-hit-aware write buffer (TAP) with low-power-state-based techniques for further power and temperature reduction, namely, TAP-low. Our experiments show that a system with TAP-low could reduce the total DRAM power consumption by up to 68.6% (19.9% on average). The steady-state temperature can be reduced by as much as 7.84??C and 2.55??C on average across eight representative workloads.
Keywords :
DRAM chips; buffer circuits; integrated circuit modelling; low-power electronics; adaptive power management; adaptive temperature management; high-performance DRAMs; low-power-state-based techniques; power consumption; steady-state temperature; throughput-aware page-hit-aware write buffer; write operations; DRAM; power; temperature;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2014842
Filename :
5075522
Link To Document :
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