CMOS Bandgap References With Self-Biased Symmetrically Matched Current–Voltage Mirror and Extension of Sub-1-V Design

Author

Lam, Yat-Hei ; Ki, Wing-Hung

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

18

Issue

6

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

857

Lastpage

865

Abstract

A series of bandgap references (BGRs) using a self-biased symmetrically matched current-voltage mirror (SM CVM) in reducing systematic offset, thus achieving an excellent line regulation, is presented. By replacing the operational amplifier with a CVM in the feedback loop, current consumption is much reduced. An SM buffer stage that is capable of driving a resistive load with minor degradation in temperature coefficient (TC) and line regulation is also presented. The technique is extended to design a sub-1-V BGR with a TC-cancellation output buffer. All circuits are designed using a 0.35- CMOS process, and experimental results are presented, confirming the analysis.

Keywords

CMOS integrated circuits; buffer circuits; CMOS bandgap references; SM buffer stage; feedback loop; resistive load; self-biased symmetrically matched current-voltage mirror; size 0.35 mum; symmetrically matched current-voltage mirror; temperature coefficient; voltage 1 V; Bandgap reference (BGR); CMOS; line regulation; self-biased; symmetrical matching (SM);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2009.2016204

Filename

5075524