DocumentCode :
1074545
Title :
A quaternary partial-response class-IV transceiver for 125 Mbit/s data transmission over unshielded twisted-pair cables: principles of operation and VLSI realization
Author :
Cherubini, Giovanni ; Olcer, S. ; Ungerboeck, Gottfried
Author_Institution :
Res. Div., IBM Zurich Res. Lab., Ruschlikon
Volume :
13
Issue :
9
fYear :
1995
fDate :
12/1/1995 12:00:00 AM
Firstpage :
1656
Lastpage :
1669
Abstract :
The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of ±100 ppm. The implementation of all digital signal-processing functions in a single 0.5 μm CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements
Keywords :
CMOS digital integrated circuits; FDDI; VLSI; adaptive equalisers; analogue-digital conversion; crosstalk; data communication; data communication equipment; digital signal processing chips; digital-analogue conversion; interference suppression; maximum likelihood detection; multiplexing; multiplexing equipment; partial response channels; spectral analysis; telecommunication signalling; transceivers; twisted pair cables; 0.5 micron; 125 Mbit/s; 6 W; CMOS VLSI prototype chip; EMC regulations; FDDI network; NEXT cancellation; VLSI realization; adaptive NEXT cancellation; adaptive equalizer; analog-to-digital conversion; digital signal-processing functions; digital-to-analog conversion; elastic buffer; fiber distributed data interface; full-duplex transmission; maximum-likelihood sequence detection; near-end crosstalk; phase drift; power consumption; quaternary partial-response class-IV transceiver; signaling; unshielded twisted-pair cables; Cables; Clocks; Crosstalk; Energy consumption; FDDI; Maximum likelihood detection; Spectral shape; Timing; Transceivers; Transmitters;
fLanguage :
English
Journal_Title :
Selected Areas in Communications, IEEE Journal on
Publisher :
ieee
ISSN :
0733-8716
Type :
jour
DOI :
10.1109/49.475538
Filename :
475538
Link To Document :
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