An experimental study of the BO-MOS dynamic RAM cell

Author

Sakurai, Junji

Author_Institution

Fujitsu Limited, Kawasaki, Japan

Volume

28

Issue

10

fYear

1981

fDate

10/1/1981 12:00:00 AM

Firstpage

1178

Lastpage

1182

Abstract

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N⁺diffusion. This three-dimensional structure results in a cell size of $6F^{2}$ with a minimum feature size $F$ and the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented with $F = 4$ -µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.

Keywords

Boron; Capacitance; DRAM chips; Epitaxial layers; Fabrication; Impurities; MOS capacitors; MOSFET circuits; Read-write memory; Substrates;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/T-ED.1981.20507

Filename

1481659