Title :
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
Author :
Kang-Deog Suh ; Suh, Byung-Hoom ; Lim, Young-Ho ; Kim, Jin-Ki ; Choi, Young-Joon ; Koh, Yong-Nam ; Lee, Sung-Soo ; Suk-Chon, Suk-Chon ; Choi, Byung-Soon ; Yum, Jin-Sun ; Choi, Jung-Hyck ; Kim, Jang-Race ; Lim, Hyung-Kyu
Author_Institution :
Sumsung Electronics Co. Ltd., Kyungki-Do, South Korea
fDate :
11/1/1995 12:00:00 AM
Abstract :
While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm2 die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA
Keywords :
CMOS memory circuits; EPROM; NAND circuits; 0.5 micron; 0.8 mA; 2.3 MByte/s; 24 MByte/s; 25 ns; 3.3 V; 32 Mbit; CMOS technology; NAND flash memory; boosted wordline; burst cycle time; cost; die size; incremental step pulse programming; interleaved data paths; mass storage; process variation tolerance; self boosted program inhibit voltage; yield; CMOS process; CMOS technology; Charge pumps; Costs; Energy consumption; Flash memory; Hard disks; Performance gain; Solid state circuits; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
