A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

Author

Iwata, Yoshihisa ; Imamiya, Ken-ichi ; Sugiura, Yoshihisa ; Nakamura, Hiroshi ; Oodaira, Hideko ; Momodomi, Masaki ; Itoh, Yasuo ; Watanabe, Toshiharu ; Araki, Hitoshi ; Narita, Kazuhito ; Masuda, Kazunori ; Miyamoto, J.-I.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

Volume

30

Issue

11

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

1157

Lastpage

1164

Abstract

A 32 Mb NAND type flash EEPROM has been developed with 0.425 μm CMOS technology. A 35 ns cycle time is achieved by adopting a pipeline scheme. A boosted word-line scheme and a program verify operation achieving tight threshold voltage (Vth) distribution of programmed cells reduce read-out access time. Multiple block erase operation is realized by adopting erase block registers. All functions are operable with a single 5.3 V or 5 V power supply

Keywords

CMOS memory circuits; EPROM; NAND circuits; pipeline processing; 0.425 micron; 3.3 V; 32 Mbit; 35 ns; 5 V; CMOS technology; NAND flash EEPROM; boosted word-line scheme; erase block registers; multiple block erase operation; pipeline scheme; program verify operation; read-out access time; threshold voltage distribution; CMOS logic circuits; CMOS technology; Circuit noise; EPROM; Noise reduction; Pipelines; Power supplies; Registers; Semiconductor device noise; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.475702

Filename

475702