An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Author

Sakata, Takeshi ; Hor, Masashi ; Sekiguch, Tomonori ; Ueda, Shigeki ; Tanaka, Hitoshi ; Yamasaki, Eiji ; Nakagome, Yoshinobu ; Aoki, Masakazu ; Kaga, Toru ; Ohkura, Makoto ; Nagai, Ryo ; Murai, Fumio ; Tanaka, Toshihiko ; Iijima, Shimpei ; Yokoyama, Natsu

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

30

Issue

11

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

1165

Lastpage

1173

Abstract

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-μm CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply

Keywords

CMOS memory circuits; DRAM chips; distributed memory systems; memory architecture; 0.16 micron; 1 Gbit; 1.5 V; 220 MHz; CMOS process; DRAM; I/O block; burst-mode cycle time; distributed-column-control architecture; event-driven circuits; subarrays; synchronous operation; wiring delay; Circuits; Clocks; Delay; Frequency; Graphics; HDTV; Pipelines; Random access memory; Timing; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.475703

Filename

475703