Title :
A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current
Author :
Yamauchi, Hiroyuki ; Iwata, Toru ; Uno, Akito ; Fukumoto, Masanori ; Fujita, Tsutomu
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fDate :
11/1/1995 12:00:00 AM
Abstract :
A 16M self-refresh DRAM achieving less than 0.5 μA per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a VBB pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 μA per megabyte. Furthermore, the addition of a gate-received VBB detector (GRD) reduces dc retention current to less than 0.1 μA per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery
Keywords :
DRAM chips; 16 Mbit; 2.5 year; button-shaped lithium battery; circuit technology; data-retention current; data-retention time; gate-received detector; plate-floating leakage-monitoring; pull-down word-line driver; relaxed junction biasing; self-refresh DRAM; Batteries; Detectors; Driver circuits; Lithium; Monitoring; Random access memory; Testing; Time measurement; Variable structure systems; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
