DocumentCode
1075812
Title
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL
Author
Ishibashi, Koichiro ; Komiyaji, Kunihiro ; Toyoshima, Hiroshi ; Minami, Masataka ; Ohki, Nagatoshi ; Ishida, Hiroshi ; Yamanaka, Toshiaki ; Nagano, Takahiro ; Nishida, Takashi
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Volume
30
Issue
11
fYear
1995
fDate
11/1/1995 12:00:00 AM
Firstpage
1189
Lastpage
1195
Abstract
A 4-Mb (64 k×64) synchronous wave-pipeline CMOS SRAM is fabricated by 0.25-μm CMOS technology. Multiphase active pulse control (MPAC) enables fully random 300 MHz operation at 2.5 V, resulting in a bandwidth of 2.4 GB/s. The pulse is generated by multiphase PLL (MPPLL) using an array oscillator with current consumption of 7.5 mA
Keywords
CMOS memory circuits; SRAM chips; phase locked loops; pipeline processing; 0.25 micron; 2.5 V; 300 MHz; 4 Mbit; 7.5 mA; array oscillator; multiphase PLL; multiphase active pulse control; synchronous static RAM; wave-pipeline CMOS SRAM; Bandwidth; Decoding; Frequency; Latches; Phase locked loops; Pipelines; Pulse amplifiers; Pulse circuits; Pulse generation; Random access memory;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.475706
Filename
475706
Link To Document