Title :
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors
Author :
Okamura, Hitoshi ; Toyoshima, Hideo ; Takeda, Koichi ; Oguri, Takashi ; Nakamura, Satoshi ; Takada, Masahide ; Imai, Kiyotaka ; Kinoshita, Yasushi ; Yoshida, Hiroshi ; Yamazaki, Toru
Author_Institution :
Bipolar ASIC Dept., NEC Corp., Kawasaki, Japan
fDate :
11/1/1995 12:00:00 AM
Abstract :
While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology
Keywords :
BiCMOS memory circuits; CMOS memory circuits; SRAM chips; 0.4 micron; 1 W; 1 ns; 2.5 V; 32 Kbit; BiCMOS technology; CMOS memory cell; NTL decoder; NTL-CMOS SRAM macro; PMOS access transistors; automatic bit line signal voltage swing controller; nonthreshold logic; onchip voltage generator; BiCMOS integrated circuits; Bipolar transistors; Decoding; Delay lines; Driver circuits; Inverters; Logic; MOSFETs; Random access memory; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
