Author :
Miyano, Shinji ; Numata, Kenji ; Sato, Katsuhiko ; Yabe, Tomoaki ; Wada, Masaharu ; Haga, Ryo ; Enkaku, Motohiro ; Shiochi, Masazumi ; Kawashima, Yutaka ; Iwase, Masayuki ; Ohgata, Masahisa ; Kumagai, Junpei ; Yoshida, Takeshi ; Sakurai, Masaomi ; Kaki, S
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
An 8 Mb embedded DRAM has been developed. The salient feature of this embedded DRAM is page fault tolerance. Accessing across different pages can be performed using a minimum column cycle. This feature is achieved by placing a data latch and a transfer gate between the bit line sense amplifier and the column select gate. This DRAM can be reconfigured as separated 2 Mb units when it is embedded as a macro cell of an ASIC library
Keywords :
DRAM chips; fault tolerant computing; 1.6 Gbyte/s; 8 Mbit; ASIC library; bit line sense amplifier; bit line separation gate; column select gate; data latch; data transfer rate; embedded DRAM; macro cell; minimum column cycle; page fault tolerance; reconfiguration; transfer gate; Application specific integrated circuits; Bandwidth; Fault tolerance; Graphics; Laboratories; Latches; Libraries; Packaging; Random access memory; Semiconductor devices;
