Title :
An experimental 295 MHz CMOS 4K×256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers
Author :
Kushiyama, Natsuki ; Tan, Charles ; Clark, Richard ; Lin, Jane ; Perner, Fred ; Martin, Lisa ; Leonard, Mark ; Coussens, Gene ; Cham, Kit
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kanagawa, Japan
fDate :
11/1/1995 12:00:00 AM
Abstract :
An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differential I/O buses, laid out in fourth metal over the memory cell arrays, use a 0.3 V differential swing. The SRAM is fabricated in a 0.35 μm four-layer metal CMOS process employing a 6-T SRAM cell measuring 5.2 μm×6.6 μm. The die measures 13.22 mm×4.80 mm. The SRAM operates at 295 MHz with a 3.3 V supply, achieving a bandwidth of 9.44 Gbyte/s
Keywords :
CMOS memory circuits; SRAM chips; 0.35 micron; 256 bit; 295 MHz; 3.3 V; 6-T SRAM cell; bandwidth; bidirectional read/write shared sense amps; die size; four-layer metal CMOS process; fully differential I/O buses; memory cell arrays; power consumption; self-timed pulsed word-line drivers; synchronous SRAM; Bandwidth; CMOS process; Circuits; Clocks; Companies; Decoding; Laboratories; Pipelines; Pulse amplifiers; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
