A 0.07 mm $^2$ Asynchronous Logic CMOS Pulsed Receiver Based on Radio Events Self-Synchronization

This paper presents an ultra-low-power radio receiver implemented only with CMOS logic gates used as basic building blocks and proves its operation. The self-timed duty-cycled system is self-synchronized with the input radio signal, runs a noise-robust baseband detection and does not require any reference besides power supply. Based on S-OOK modulation, the 350-450 MHz digital radio RX occupies an area of 0.07 mm ² in a 130 nm RFCMOS technology and achieves a 0.1% sensitivity of -63 dBm at 95 kbps, 380 MHz center frequency and 40 μW active power consumption at 1.1 V power supply. At 1.0 V it achieves -62 dBm sensitivity and 33 μW active power at ~ 0.1% error rate. The compact receiver, whose architecture is parametric and technology scalable, suits energy harvested and miniaturized biomedical applications. The paper also presents the potential advantages of asynchronous logic pulse radio and introduces an ad-hoc VHDL model demonstrating RTL-/gate-level accurate error-rate predictions capabilities based on digital simulation only, i.e., without requiring electrical-level co-simulation.