A High-Speed Low-Distortion CMOS Source Follower Buffer

Author

Campos, M.V. ; Filho, C.A.R.

Author_Institution

Univ. Estadual de Montes Claros (UNIMONTES), Montes Claros, Brazil

Volume

11

Issue

2

fYear

2013

fDate

Mar-13

Firstpage

677

Lastpage

681

Abstract

This paper discusses the design and implementation of a pseudo-differential high-speed and highly linear novel Source-Follower Buffer in 0.35 μm CMOS. The high linearity of Source Follower is achieved by means of a cascode transistor and an auxiliary structure to mitigate impact of channel modulation and parasitic capacitances. The new architecture consumes 10 mW from a 3.3-V supply and it achieves a total harmonic distortion of -74.5 dB at 100 MHz, yielding 12-b resolution. Design methodology, simulation and experimental results are presented.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; harmonic distortion; transistors; cascode transistor; channel modulation; frequency 100 MHz; high-speed low-distortion CMOS source follower buffer; highly linear novel source-follower buffer; parasitic capacitances; power 10 mW; pseudo-differential high-speed buffer; size 0.35 mum; total harmonic distortion; voltage 3.3 V; CMOS integrated circuits; Conferences; Irrigation; MOS devices; Total harmonic distortion; Transistors; A/D Converters; Linearity; Source Follower; Total Harmonic Distortion;

fLanguage

English

Journal_Title

Latin America Transactions, IEEE (Revista IEEE America Latina)

Publisher

ieee

ISSN

1548-0992

Type

jour

DOI

10.1109/TLA.2013.6533954

Filename

6533954