Alignment signals from resist-coated marks for direct wafer writing

Monte Carlo (MC) calculations based on a continuous-slowing-down approximation and experimental techniques are used to characterize the backscattered alignment signals from resist-covered Si tapered step marks. Effects of the coated thickness and the resist profile slope are separated by using MC simulation. A 1-µm resist coating on a 2-µm Si step reduces the maximum difference in the back-scattered signal for 20-keV electrons by a factor of 2 and about ⅓ of this reduction is due to the fact that the resist does not conformally follow the step. The rate of reduction in with resist coating was found to be faster for signals collected from low takeoff angles, however, the low takeoff angle signals are still preferred. For a 1-µm resist coating and 20-keV electrons, backscattered electrons with less than half the incident energy contain more information about the substrate but the use of energy analysis techniques would only improve the contrast slightly with a tradeoff in reduced signal-to-noise ratio. For best results alignment marks should a) be covered by a resist thickness less than 0.4 RB(RB= Bethe range) so that electrons will "see" the underlying material, and b) have a depth larger than ⅓ the resist thickness, so that the resist profiles will adequately reflect the underlying mark topography.