Simulation of an optimized electron-beam lithographic process

A methodology is developed to define design ground rules for an electron-beam direct write lithographic process for very high density circuits, using a computer simulation program to quantify the tradeoffs among various resist process variables for 1.5-µm minimum feature sizes. An iterative procedure is used to obtain a set of coefficients for a proximity correction algorithm which minimizes the pattern-dependent linewidth variations. Finally, the total linewidth tolerance for this technology is estimated.