Title :
High-density zero suppressor and encoder VME board using field programmable gate array
Author :
Aloisio, A. ; Cevenini, F. ; Patricelli, S. ; Parascandolo, P.
Author_Institution :
Dipartimento di Sci. Fisiche, Naples Univ., Italy
fDate :
2/1/1994 12:00:00 AM
Abstract :
We describe a 96 bit zero-suppressor and encoder VME board designed for the RPC trigger system of the L3 Forward/Backward Muon detector at CERN. Running at 20 MHz clock frequency, the board processes the elementary 96 bit wide detector pattern in less than one microsecond, storing hit addresses in a FIFO array. Details of the board architecture based on seven XILINX XC3020 LCAs-are presented and simulation and preliminary test results are briefly reported
Keywords :
detector circuits; digital integrated circuits; encoding; logic arrays; nuclear electronics; printed circuit design; trigger circuits; 1 mus; 20 MHz; FIFO; L3 Forward/Backward Muon detector; RPC trigger; VME board; XILINX XC3020; architecture; encoder; field programmable gate array; resistive plate counter trigger; zero suppressor; Clocks; Cosmic rays; Costs; Counting circuits; Detectors; Field programmable gate arrays; Frequency; Mesons; Sensor arrays; Testing;
Journal_Title :
Nuclear Science, IEEE Transactions on
