DocumentCode
1076969
Title
Oxide isolated ISL technologies
Author
Lohstroh, J. ; Crommenacker, J.D.P.v.d. ; Linssen, A.J.
Author_Institution
Philips Research Laboratories, Eindhoven, Netherlands
Volume
2
Issue
2
fYear
1981
fDate
2/1/1981 12:00:00 AM
Firstpage
30
Lastpage
31
Abstract
Using oxide isolation, ISL gates can be fabricated without the relative slow lateral pnp transistor which is inevitable in pn-isolated processes. Now the clamping action is provided either by a fast vertical pnp only, or a reverse operated npn. Using a 1.2 µm thick epilayer and 3 µm minimum dimensions, propagation delay times of 0.7 ns are obtained at a current level of 200 µA per gate.
Keywords
Capacitance; Clamps; Driver circuits; Energy consumption; Epitaxial layers; Isolation technology; Logic devices; Propagation delay; Schottky diodes; Very large scale integration;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1981.25329
Filename
1481813
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