• DocumentCode
    1077076
  • Title

    Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate

  • Author

    Srivastava, Navin ; Suaya, Roberto ; Banerjee, Kaustav

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA
  • Volume
    28
  • Issue
    7
  • fYear
    2009
  • fDate
    7/1/2009 12:00:00 AM
  • Firstpage
    1047
  • Lastpage
    1060
  • Abstract
    We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green´s function approach with the correct quasi-static limit, a modified discrete complex images approximation to the Green´s function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances that are relevant to VLSI interconnects. This approach permits the evaluation of the self-impedance and mutual-impedance of multi-conductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multilayer substrate.
  • Keywords
    Green´s function methods; VLSI; electric impedance; integrated circuit interconnections; millimetre wave integrated circuits; multilayers; 2-D Green function; CPU time reduction; continuous dipole expansion; electromagnetic parameters; high-frequency VLSI interconnect; impedance extraction; modified discrete complex images approximation; multiconductor current loops; multilayer conductive substrate; mutual impedance; self-impedance; substrate effects; Green´s function; VLSI interconnect; high frequency; impedance; magnetic dipole; parasitic extraction; substrate;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2009.2017432
  • Filename
    5075816