Title :
A Novel Table-Based Approach for Design of FinFET Circuits
Author :
Thakker, Rajesh A. ; Sathe, Chaitanya ; Sachid, Angada B. ; Baghini, Maryam Shojaei ; Rao, V. Ramgopal ; Patil, Mahesh B.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay
fDate :
7/1/2009 12:00:00 AM
Abstract :
A new lookup-table (LUT) approach, based on normalization of the drain current with an I D-V G template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.
Keywords :
MOSFET circuits; circuit optimisation; integrated circuit design; integrated circuit modelling; table lookup; FinFET circuit design; MOS transistor circuit; integrated circuit optimization; lookup-table approach; mixed-mode simulation; Circuit design; FinFET; hierarchical particle swarm optimization (PSO); lookup table (LUT);
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2009.2017431
