• DocumentCode
    1077439
  • Title

    Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit

  • Author

    Ino, M. ; Kurumada, K. ; Ohmori, M.

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    2
  • Issue
    6
  • fYear
    1981
  • fDate
    6/1/1981 12:00:00 AM
  • Firstpage
    144
  • Lastpage
    146
  • Abstract
    The margin of threshold voltage (VT) for GaAs normally-off MESFET DCFL´s was numerically analyzed applying the equivalent inverter circuit model. The results show that the optimum (VT) is 0.3 V. Quantitative relation between the margin and delay time is obtained as a function of (VT). At (VT) = 0.3 V, the margin is 0.28 V with tpdless than 100 ps for 0.5 µm gate length.
  • Keywords
    Circuit simulation; Delay effects; Doping; Electron mobility; Gallium arsenide; Inverters; MESFET circuits; Parasitic capacitance; Semiconductor process modeling; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1981.25375
  • Filename
    1481859
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1077439