DocumentCode :
107870
Title :
A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity
Author :
Rahman, Manzur ; Sanyal, Arindam ; Nan Sun
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
Volume :
62
Issue :
5
fYear :
2015
fDate :
May-15
Firstpage :
426
Lastpage :
430
Abstract :
This brief presents a fast-converging hybrid successive approximation register (SAR) analog-to-digital converter (ADC) based on the radix-3 and radix-2 search approaches. The radix-3 approach achieves 1.6 bits/cycle, and the radix-2 approach mitigates the effect of comparator offset and improves the accuracy of the ADC. Incorporating clock gating of comparators and efficient switching of capacitors, the proposed hybrid ADC demonstrates promising balance between hardware complexity and speed and can achieve equivalent signal-to-noise-and-distortion-ratio (SNDR) with less capacitors compared with radix-3 SAR ADC. Behavioral simulation-based results verify operation and merit of the proposed architecture. An 11-bit 45-MS/s prototype with 5% capacitor mismatch in 180-nm CMOS was simulated in SPICE and achieves 67 dB of SNDR after calibration.
Keywords :
analogue-digital conversion; comparators (circuits); digital arithmetic; analog-to-digital converter; clock gating; comparator offset; fast-converging hybrid successive approximation register; hybrid radix-2 SAR ADC; hybrid radix-3 SAR ADC; size 180 nm; Calibration; Capacitors; Circuits and systems; Complexity theory; Hardware; Linearity; Switches; Analog-to-digital converter (ADC); digital-to-analog converter (DAC); successive approximation register (SAR);
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2014.2385214
Filename :
6996009
Link To Document :
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