Title :
Transient simulation of wire pull test on Cu/low-K wafers
Author :
Yeh, Chang-Lin ; Lai, Yi-Shao ; Kao, Chin-Li
Author_Institution :
Stress-Reliability Lab., Adv. Semicond. Eng. Inc., Kaohsiung
Abstract :
This paper focuses on the numerical analysis of pull test reliability of gold wires bonded on the Cu/low-K wafer. Prior to wire pull, transient analysis of the complete wirebonding process, which involves both impact and ultrasonic vibration stages, is performed to allocate residual stresses within the wire and the Cu/low-K structure. After wirebonding, fracturing of the wire subjected to a pull load is modeled using the eroding technique so that failure patterns and bonding strength of the wire can be investigated. The analysis applies the explicit time integration scheme, which is feasible in dealing with nonlinear transient structural behavior. Parametric studies show that as the yield stress of the low-K material decreases, the pull force reduces significantly. Furthermore, the pull force increases as the bond force increases but not very significantly
Keywords :
circuit reliability; copper; gold; integration; internal stresses; lead bonding; low-k dielectric thin films; transient analysis; bonding strength; eroding technique; explicit time integration; failure patterns; finite-element analysis; impact vibration; low-k material; low-k wafers; nonlinear transient structural behavior; numerical analysis; pull test reliability; residual stresses; transient analysis; ultrasonic vibration; wire pull test transient simulation; wirebonding process; yield stress; Gold; Load modeling; Numerical analysis; Parametric study; Residual stresses; Semiconductor device modeling; Testing; Transient analysis; Wafer bonding; Wire; Cu/low-K; finite-element analysis; wire pull test; wirebonding;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2006.875081