DocumentCode
1078782
Title
Process design using two-dimensional process and device simulators
Author
Chin, Daeje ; Kump, Michael R. ; Lee, Hee-Gook ; Dutton, Robert W.
Author_Institution
Stanford University, Stanford, CA
Volume
29
Issue
2
fYear
1982
fDate
2/1/1982 12:00:00 AM
Firstpage
336
Lastpage
340
Abstract
A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.
Keywords
Boron; Capacitance; Impurities; Ion implantation; MOS devices; Numerical simulation; Oxidation; Process design; Testing; Topology;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1982.20704
Filename
1482201
Link To Document