DocumentCode :
1079383
Title :
TITAC: design of a quasi-delay-insensitive microprocessor
Author :
Nanya, Takashi ; Ueno, Yoichiro ; Kagotani, Hiroto ; Kuwako, Masashi ; Takamura, Akihiro
Author_Institution :
Tokyo Inst. of Technol., Japan
Volume :
11
Issue :
2
fYear :
1994
Firstpage :
50
Lastpage :
63
Abstract :
TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.<>
Keywords :
logic design; microprocessor chips; sequential circuits; 8 bit; TITAC; asynchronous; binary decision diagram; event-driven; isochronic-forks assumption; multilevel AND-OR; quasi-delay-insensitive microprocessor; von Neumann microprocessor; Asynchronous circuits; CMOS technology; Clocks; Delay; Digital systems; Logic design; Microprocessors; Signal design; Timing; Wire;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/54.282445
Filename :
282445
Link To Document :
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