• DocumentCode
    1079401
  • Title

    A 16K-bit static IIL RAM with 25-ns access time

  • Author

    Inabe, Yasunobu ; Hayashi, Toshio ; Kawarada, Kuniyasu ; Miwa, Hideo ; Ogiue, Katsumi

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    29
  • Issue
    4
  • fYear
    1982
  • fDate
    4/1/1982 12:00:00 AM
  • Firstpage
    695
  • Lastpage
    700
  • Abstract
    A 16 384 × 1-bit RAM with 25-ns access time, 600-mW power dissipation, and 33-mm2chip size has been developed. Excellent speed-power performance with high packing density has been achieved by an oxide isolation technology in conjunction with novel ECL circuit techniques and IIL flip-flop memory cells, 980 µm2(35 µm × 28 µm) in cell size. Development results have shown that IIL flip-flop memory cell is a trump card for assuring achievement of a high-performance large-capacity bipolar RAM, in the above 16K-bit/chip area.
  • Keywords
    Circuit synthesis; Delay; Flip-flops; Isolation technology; Laboratories; Power dissipation; Random access memory; Read-write memory; Telegraphy; Telephony;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1982.20764
  • Filename
    1482261
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1079401