SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C_j) has been reduced in SODEL FET, i.e., C_j (area) was ∼0.73 fF/μm² both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient γ is also reduced to less than 0.02 V¹2/. Nevertheless, current drives of 886 μA/μm (I_off=15 nA/μm) in nFET and -320 μA/μm (I_off=10 nA/μm) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V_dd|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.