DocumentCode
1079890
Title
A Predictive Shutdown Technique for GPU Shader Processors
Author
Wang, Po-Han ; Chen, Yen-Ming ; Yang, Chia-Lin ; Cheng, Yu-Jung
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei
Volume
8
Issue
1
fYear
2009
Firstpage
9
Lastpage
12
Abstract
As technology continues to shrink, reducing leakage is critical to achieve energy efficiency. Previous works on low-power GPU (graphics processing unit) focus on techniques for dynamic power reduction, such as DVFS (Dynamic Voltage/Frequency Scaling) and clock gating. In this paper, we explore the potential of adopting architecture-level power gating techniques for leakage reduction on GPU. In particular, we focus on the most power-hungry components, shader processors. We observe that, due to different scene complexity, the required shader resources to satisfy the target frame rate actually vary across frames. Therefore, we propose the predictive shader shutdown technique to exploit workload variation across frames for leakage reduction on shader processors. The experimental results show that predictive shader shutdown achieves up to 46% leakage reduction on shader processors with negligible performance degradation.
Keywords
computer architecture; computer graphic equipment; coprocessors; power aware computing; GPU shader processors; architecture-level power gating techniques; clock gating; dynamic power reduction; dynamic voltage-frequency scaling; graphics processing unit; predictive shader shutdown technique; Energy-aware systems; Low-power design;
fLanguage
English
Journal_Title
Computer Architecture Letters
Publisher
ieee
ISSN
1556-6056
Type
jour
DOI
10.1109/L-CA.2009.1
Filename
4758617
Link To Document