Analysis of nonlinearities in MOS floating resistor networks

Author

Wilson, G. ; Chan, P.K.

Author_Institution

Sch. of Electron. Commun. & Electr. Eng., Plymouth Univ., UK

Volume

141

Issue

2

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

82

Lastpage

88

Abstract

Expressions for the linearised V/I characteristics of a group of floating resistor structures employing MOS transistors operating in the triode mode are presented. Mobility-degradation effects are accurately modelled and identified as the major residual distortion source in most configurations. The application of common-mode signals to the gate and substrate terminals of a single device is shown to produce a benchmark linearisation performance. Geometrical mismatches are identified as having a potentially dominant influence on the extent to which second-harmonic distortion is suppressed

Keywords

buffer circuits; carrier mobility; field effect transistor circuits; linearisation techniques; nonlinear network analysis; resistors; MOS floating resistor network nonlinearities analysis; MOS transistors; benchmark linearisation performance; buffers; common-mode signals; gate terminals; geometrical mismatches; linearised V/I characteristics; mobility-degradation effects; residual distortion source; second-harmonic distortion suppression; substrate terminals; triode mode;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19949837

Filename

282623