Analyzing ECL´s noise margin

Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit configurations. A key advantage of the ECL/CML circuit configuration is its ability to operate reliably at low voltage swings. There is, however, a trade-off: as the voltage swing is reduced, so also is the ability of the circuit to withstand unwanted input voltage variations, i.e., noise. While the speed and power dissipation characteristics of ECL/CML have received considerable analytical and quantitative treatment in the literature, the noise margin has earned little analytical attention. In this article, the authors derive an improved expression for the static noise margin of ECL.<>