• DocumentCode
    1080466
  • Title

    Latch up in physically merged bipolar-MOS BiCMOS structures

  • Author

    Liang, Shunlin ; Gu, T. ; Salama, C.A.T.

  • Author_Institution
    Dept. of Electr. Eng., Toronto Univ., Ont., Canada
  • Volume
    27
  • Issue
    13
  • fYear
    1991
  • fDate
    6/20/1991 12:00:00 AM
  • Firstpage
    1124
  • Lastpage
    1126
  • Abstract
    A two-dimensional numerical simulation study of latch up in merged bipolar-MOS structures for BiCMOS applications is presented. The results of the simulations indicate that special precautions must be exercised in designing merged transistor structures for these applications.
  • Keywords
    BIMOS integrated circuits; electrical faults; semiconductor device models; simulation; BiCMOS; latch up; latchup simulation; merged bipolar-MOS structures; merged transistor structures; two-dimensional numerical simulation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19910702
  • Filename
    132704
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1080466