Title :
Latch up in physically merged bipolar-MOS BiCMOS structures
Author :
Liang, Shunlin ; Gu, T. ; Salama, C.A.T.
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fDate :
6/20/1991 12:00:00 AM
Abstract :
A two-dimensional numerical simulation study of latch up in merged bipolar-MOS structures for BiCMOS applications is presented. The results of the simulations indicate that special precautions must be exercised in designing merged transistor structures for these applications.
Keywords :
BIMOS integrated circuits; electrical faults; semiconductor device models; simulation; BiCMOS; latch up; latchup simulation; merged bipolar-MOS structures; merged transistor structures; two-dimensional numerical simulation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19910702
