Title :
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs
Author :
Ciesielski, Maciej ; Kalla, Priyank ; Askar, Serkan
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA
Abstract :
A Taylor expansion diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated
Keywords :
data flow computing; data flow graphs; equivalence classes; formal verification; hardware description languages; HDL design specification; TED canonical graph based representation; Taylor expansion diagrams; Taylor series; algebraic symbols; data flow design verification; decomposition scheme; equivalence verification; multivariate polynomial; word-level signal model; Algorithm design and analysis; Boolean functions; Data flow computing; Data structures; Hardware design languages; Polynomials; Process design; Signal design; Signal processing algorithms; Taylor series; Register transfer level—design aids; arithmetic and logic structures—verification; symbolic and algebraic manipulation.; verification;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2006.153