DocumentCode
1081133
Title
On-chip capacitance measurement circuits in VSLI structures
Author
Iwai, Hiroshi ; Kohyama, Susumu
Author_Institution
Toshiba Corporation, Kawasaki-shi, Kanagawa, Japan
Volume
29
Issue
10
fYear
1982
fDate
10/1/1982 12:00:00 AM
Firstpage
1622
Lastpage
1626
Abstract
A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.
Keywords
Capacitance measurement; Capacitors; Circuit testing; Geometry; Large scale integration; Parasitic capacitance; Semiconductor device measurement; Very large scale integration; Voltage; Wiring;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1982.20924
Filename
1482421
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