DocumentCode
1081280
Title
Memory Subsystems in High-End Routers
Author
Wang, Feng ; Hamdi, Mounir
Author_Institution
Hong Kong Univ. of Sci. & Technol., Hong Kong
Volume
29
Issue
3
fYear
2009
Firstpage
52
Lastpage
63
Abstract
As Internet routers scale to support next-generation networks, their memory subsystems must also scale. Several solutions combine static RAM and dynamic RAM buffering but still have major scaling limitations. Using a parallel architecture and distributed memory-management algorithms with hybrid SRAM/DRAM improves buffering performance. The parallel hybrid SRAM/DRAM memory system is also work conserving, which is particularly important under light traffic conditions.
Keywords
DRAM chips; Internet; SRAM chips; buffer storage; distributed memory systems; network routing; parallel architectures; Internet router; buffering performance; distributed memory management; dynamic RAM buffering; high-end router; memory subsystem; next-generation network; parallel architecture; parallel hybrid SRAM/DRAM memory system; static RAM buffering; Bandwidth; Buffer storage; Buildings; DRAM chips; Delay; IP networks; Intelligent networks; Next generation networking; Random access memory; Read-write memory; SRAM/DRAM; parallel distributed memory management; per-flow queues;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/MM.2009.45
Filename
5076439
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