Simulating the complexity of regular VLSI layout

Based on a hierarchical computer-aided design model, the complexity of regular integrated circuit (IC) layout is simulated by a compactness ratio approach. Using a first-order approximation and regular array models, the general expression of the compactness ratio is derived and depicted graphically. The compactness ratio varied with the line width and spacing of the submodules within a circuit and thus can be applied to essentially any IC technology. Sample MOS design results further verify that the compactness ratio and module area are inversely proportional to the number of design levels in the design hierarchy